Design of Low Power Mixcolumn in Advanced Encryption Standard Algorithm

the security data transmission algorithm in cryptography is Advanced Encryption Standard (AES). The operation mix column consumed more power in the algorithm. In this paper the power consumption of mix column is reduced in order to achive the total power consumption of AES. Using a simple exclusive OR gate that is XOR gate pass transistor logic, the power can be minimized when compare to the other methods of design the mixcolumn transformation. The design is implemented using the cadence Schematic Editor. The proposed methodology gives the low power as 3.996nW. The advantage of low power mixcolumn is playing an important role in today’s security needs like RFID tags, smart cards. Index Terms — Advanced Encryption Standard (AES), Cryptography, Encryption, low power, Mix Column architecture, Pass transistor logic.